Single-level cell (SLC) buffers may include NAND-type flash memory (“NAND memory”) that is organized into multiple cells, with each cell containing one bit of data. Tri-level cell (TLC) memory may include NAND memory that is organized into multiple cells, with each cell containing three bits of data. The number of bits per cell may generally depend on how many distinct voltage levels used during program operation(s) associated with writing to, reading from and/or erasing the cell. Thus, in the case of TLC memory, to support three bits per cell, eight voltage levels may be used to distinguish between the eight possible combinations of ones and zeros (e.g., 000, 001, 010, 011, 100, 101, 110, 111) written to the cell.
SLC buffers may generally be relatively fast to access (e.g., due to the single program voltage level), but may have a relatively low storage capacity. By contrast, TLC memory may be relatively slow to access, but may have a higher storage capacity. Recent developments in memory technology may provide for using TLC memory as part of the SLC buffer in order to avoid the slower access times associated with TLC memory. Conventional solutions, however, for converting TLC memory regions to SLC memory regions, and back again, may use inefficient conversion policies that lead to suboptimal performance and/or a failure to meet quality of service (QOS) constraints placed on the storage device.